The invention relates to a level shifter, and more particularly to a programmable level shifter.
In many logic, memory and timing arrangements, communication between functional blocks requires different driving voltages. Voltage level shifters provide an interface for output of voltage levels from one block that does not meet the voltage level requirements of an interconnected block.
FIG. 1 shows a circuit diagram of a conventional level shifter. Normally, the level shifter 1 transforms a low input voltage level Vin to a high voltage level swinging between a ground Vgnd1 and a high power supply voltage Vcc1. When the input voltage level Vin is at a low logic of approximately zero volts, for example, an N-type FET MN2 is turned off and an N-type FET MN1 is turned on. While the N-type FET MN1 is completely turned on, an output node Vo is pulled down substantially to the ground Vgnd1. In contrast to the previous example, when the input voltage level Vin is at a high logic, the output node Vo is pulled up substantially to the high power supply voltage Vcc1 while the N-type FET MN2 is completely turned on.
With respect to achieving a desired functional ability, commonly, the level shifter 1 has a predetermined ratio of a pull-up device and a pull-down device. The level shifter 1, however, may malfunction when either the input voltage level Vin or the high power supply voltage Vcc1 thereto is altered. For example, when the level shifter 1 is designed to transform a 1.8-volt voltage level to a 3.3-volt voltage level, if the level shifter 1 is disposed in a 2.5-volt IO circuit to provide a specific circuit with 2.5-volt voltage level, the output Vo thereof may not be pulled up or be pulled down substantially, thus a malfunction occurs and performance such as balanced delay time thereof would be affected. Hence, the conventional level shifter 1 is only capable of driving the specific circuit with a specific operational voltage level, affecting compatibility.